library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity corrimientoQ is
Port ( clk : in STD_LOGIC;
Qcorrizq : in std_LOGIC;
Qcorrder : in std_LOGIC;
F : in std_logic_vector (7 downto 0);
ena : in std_logic; 
Rq7 : out std_logic;
Rq0 : out std_logic;
Q: out std_logic_vector (7 downto 0));


end corrimientoQ;

architecture Behavioral of corrimientoQ is
constant s0 : std_logic := '0';

begin
process (clk,F,Qcorrder,Qcorrizq,ena)
begin
	Rq7 <= F(7);
	Rq0 <= F(0);
	IF ena ='1' then
	if rising_edge (clk) then
			if Qcorrizq = '0' and Qcorrder ='0'
				then Q <= F;
			end if;

			if Qcorrizq = '1' and Qcorrder ='0'
				then Q <= F(6 downto 0) & s0;
			end if;

			if Qcorrizq = '0' and Qcorrder ='1'
				then Q <= s0 & F(7 downto 1);
			end if;
	end if; 
	else Q <= "00000000";		
	end if;
	
	
end process;
end Behavioral;